Digital Electronics

NUMBER SYSTEMS

• Number systems
• Binary number systems
• Base Conversion methods
• Binary to Octal conversion
• Binary to Hexadecimal conversion
• Octal to Binary conversion
• Hexadecimal to Binary conversion
• Binary to Decimal conversion
• Octal to Decimal conversion
• Hexadecimal to Decimal conversion
• Decimal to Binary conversion
• Decimal to Octal conversion
• Decimal to Hexadecimal conversion
• Signed binary numbers
• Sign-magnitude representation
• Complements of numbers
• One's complement representation
• Two's complement representation
• Binary arithmetic
• Binary addition
• Binary subtraction
• Binary multiplication
• Binary division
• Subtraction using 2's complement
• Subtraction using one's complement

Codes

• Codes
• Binary code
• BCD code
• BCD addition
• BCD subtraction
• BCD subtraction using 10's complement method
• Excess-3 code
• Excess-3 addition
• Excess-3 subtraction
• Gray codes
• Gray to binary conversion
• Binary to gray code conversion
• Various binary codes
• Self-complementing codes
• Some of the weighted codes
• Alpha numeric codes
• FBCDIC code
• Error detecting and correcting codes
• Error detecting code
• Hamming code

Boolean Algebra

• Boolean Algebra
• Duality
• Postulates of Boolean Algebra
• Theorems of Boolean Algebra
• Operator Precedence
• Boolean Functions (Switching Functions)
• Min Terms & Max Terms
• Sum of Product (Min Terms)
• Product of Sum (Max Terms)
• Conversion between Canonical Forms
• Problems on SOP Terms & POS Terms
• Problems on Duals
• Simplification
• Complements of F

Logic Gates

• Digital Logic Gates
• Positive and Negative Logic
• Ex-or Function
• Properties of XOR
• Odd Functions
• Universal Gates
• NAND Circuits
• Two-Level Implementation of NAND Circuits
• Multilevel NAND Circuits
• NOR Implementation
• Using NOR Gates
• Problems and Nonimplementation

K-MAP

• Karnaugh Map Method
• Two-Variable K-Map
• Three-Variable K-Map
• Four-Variable K-Map
• Prime Implicants
• Five-Variable K-Map
• Product of Sums Simplification
• Don't Care Conditions

Tabular Method

• QUNINE-MEDUSEKEY (QM) TECHNIQUE
• SIMICYCLIC PRIME IMPLICANT TABLE

Combinational Circuits

• Combinational Logic
• Combinational Circuits
• Analysis Procedure
• Design Procedure
• Code Conversion
• Binary Adder-Subtractor
• Full Adder
• Binary Adder
• Carry Propagation
• Half-Subtractor
• Full Subtractor
• Binary Subtractor
• BCD Adder
• Magnitude Comparator
• Decoders
• Encoders
• Priority Encoders
• Multiplexers
• Demultiplexers
• Boolean Function Implementation
• Wired Logic
• Three-State Gates
• Hazards in Combinational Circuits
• Practical Aspects Related to Combinational Logic Design
• Power Dissipation
• Noise Margin & Logic Voltage Levels
• Fanin & Fanout
• Propagation Delay

Flip-Flop

• Sequential Circuits
• Storage Elements: Latches
• SR Latch
• D Latch (Transparent Latch)
• Preset and Clear Inputs
• Storage Elements: Flip-Flops
• Edge-Triggered 'D' Flip-Flop
• Other Flip-Flops
• Characteristic Table
• Characteristic Equations
• Direct Inputs
• Timing and Triggering Considerations
• Max Clock Frequency
• Excitation Table of Flip-Flop
• Clocked Flip-Flop Design
• Conversion from One Type of Flip-Flop to Another Type
• Applications of Flip-Flops

Counters

• Counters
• Synchronous Counters And Asynchronous Counters
• Asynchronous Counters
• 2-bit Ripple Up Counter
• 2-bit Ripple Down Counter
• 2-bit Ripple Up-Down Counter
• Design of Asynchronous Counter
• Design of Mod-6 Asynchronous Counter using TFFs
• Design of Mod-10 Asynchronous Counter
• Synchronous Counters
• Design of Synchronous Counters
• Design of Synchronous Mod-6 Gray Code Counter using TFFs
• Design of Synchronous Mod-6 Counter using JK Flip-Flop
• Shift Register Counter
• Ring Counter
• Twisted Ring Counter (Johnson Counter)

Registers

• Application of Flip-Flops
• Shift Registers
• Serial-in-Serial-out Shift Registers
• Serial-in-Parallel-out Shift Registers
• Parallel-in-Serial-out Shift Registers
• Parallel-in-Parallel-out Shift Registers
• Bidirectional Shift Registers
• Universal Shift Registers

Finite State Model

• Finite State Model
• State Reduction (Technique)
• State Assignment
• Synthesis of Synchronous Sequential Circuits
• Serial Binary Adder
• Sequence Detector
• Parity-Bit Generator
• Capabilities and Limitations of Finite State Machines
• Synchronous Modulo-n Counters
• Mealy Model
• Moore Model
• State Diagram

Synthesis of Synchronous Sequential Circuits

• Synthesis of Synchronous Sequential Circuits

Logic Families

• Realization of Logic Gates
• Realization of OR Gate using Diodes
• Realization of AND Gate using Diodes
• Realization of NOT Gate using Transistor
• Nor Gate using Resistor-Transistor Logic (RTL)
• Direct-Coupled Transistor Logic (DCTL) NOT Gate
• Diode-Transistor Logic (DTL) NAND Gate
• Diode-Transistor Logic (DTL) NOR Gate
• Transistor-Transistor Logic (TTL) NAND Gate
• Tolempole Output/Active Pull-Up
• CMOS Logic Families
• CMOS Inverter
• CMOS NAND Gate
• CMOS NOR Gate